Modern printed circuit assemblies continue to have a greater density of attached parts. As both the density and number of parts per circuit board increases, the number of interconnected nodes to be tested rises exponentially, but the physical access to those nodes decreases. The addition of daughter cards and sub-assemblies further compounds the problem. As circuits and circuit assemblies increase in complexity, the cost of testing these circuits and circuit assemblies, e.g., an arrangement including a motherboard and one or more daughter boards, increases as well.
Steady increases in the performance requirements of printed circuit assemblies have further complicated test hardware. For example, input/output (I/O) data interfaces often now use passive elements (such as termination resistors and coupling capacitors) to satisfy the signal integrity requirements of high-frequency data signals. Some circuits use surface mount passive devices that can be difficult to place and solder correctly given their compact size. As a result, keeping up with test requirements is expensive, particularly when it is not possible to physically access nodes to be tested (for example, when the node exists on a printed circuit board trace that is on a surface obscured by other components or boards or when the node comprises a solder joint intended to couple a small (in size) surface mount resistor). Such nodes often either are not tested at all or are tested using indirect access methods, which typically have long test times and less than ideal resolution.
Less than complete test verification of circuit assembly nodes results in uncertainty regarding the ultimate operation of the circuit assembly in its intended device. The greater number of nodes not verified increases the uncertainty of whether the circuit assembly will meet all performance expectations when in operation.
Thus, there is a need for improved systems and methods for verifying expected conditions, which address these and/or other shortcomings of the prior art.